This invention relates generally to semiconductor circuits providing electrostatic discharge (ESD) protection, and specifically to a distributed ESD protection scheme.
An integrated circuit may be subjected to an Electrostatic Discharge (ESD) event both in the manufacturing process and in the ultimate system application. The energy associated with this transient discharge can easily damage the fragile devices present in a modern integrated circuit (IC). External pins or pads form the connection points for the integrated circuit to the outside world and therefore serve as pathways for ESD events. An ESD event applied to a pad may couple a voltage exceeding a thousand volts to circuitry coupled to the pad.
In conventional IC ESD protection schemes, special clamp circuits are often used to shunt ESD current between the IC power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active metal oxide semiconductor field effect transistor (MOSFET) clamp circuit, typically consists of three functional elements: a trigger circuit, an intermediate buffer circuit, and a large MOSFET transistor. The trigger circuit is designed to respond to an applied ESD event but remain inactive during normal operation of the IC. The buffer circuit is used to amplify the trigger output in order to drive the gate terminal of the large MOSFET transistor. The large MOSFET transistor, connected between the two power supply rails, acts as the primary ESD current dissipation device in the clamp circuit. Active MOSFET clamps circuits typically rely on only MOSFET action to shunt ESD current between the rails. Since the peak current in an ESD event may be on the order of amperes, very large MOSFET transistor sizes are required
A known transient-triggered active MOSFET ESD clamp circuit 10 is shown in FIG. 1. The clamp circuit 10 in FIG. 1 protects a VDD power supply rail 1 from positive ESD events referenced to a grounded VSS power supply rail 2. As shown in FIG. 1 clamp circuit 10 employs a trigger circuit 8, a buffer circuit 3, and a large N-channel MOSFET (NMOSFET) transistor 4. Trigger circuit 8 is designed as a resistor-capacitor (RC) transient detector, utilizing resistor 6 and capacitor 7. In response to an ESD event that induces a rapid positive voltage increase on the VDD rail 1, trigger circuit 8 initially holds a node 5 well below VDD. The buffer circuit 3, with an input connected to node 5, then drives the gate of NMOSFET 4 to VDD, thereby turning on the device. Once turned on, NMOSFET 4 acts as a low resistance shunt between the VDD rail land the VSS rail 2. NMOSFET 4 will remain conductive for a period of time which is determined by the RC time constant of trigger circuit 8. As a result, this RC time constant should be set long enough to exceed the maximum expected duration of an ESD event, typically three to five hundred nanoseconds, while short enough to avoid false triggering of the clamp circuit during normal ramp-up of the VDD power rail. This VDD ramp-up during normal operation typically requires two to five milliseconds. Note that once VDD reaches a constant power supply level, NMOSFET 4 is biased in a nonconductive state as required for normal operation.
A limitation with the clamp circuit of prior art FIG. 1 is that such a clamp circuit encompasses a large substrate area. It is typical for such a clamp circuit to occupy an area comparable to a wire bond pad. The large size of NMOSFET 4 in FIG. 1 is unavoidable since the performance of an active MOSFET ESD clamp circuit is directly proportional to the channel width (dimension perpendicular to current flow) of this device. In a typical implementation, NMOSFET 4 in FIG. 1 may be sized with a channel width of approximately 2000 microns. Other portions of the clamp circuit, particularly the trigger circuit 8, also occupy a significant portion of the overall clamp area. The area utilized by trigger circuit 8, including resistor 6 and capacitor 7 commonly represents up to 50 percent of the total clamp circuit area. Trigger circuit 8 requires this significant area in order to achieve the required RC time constant of three to five hundred nanoseconds.
The large size of the active MOSFET ESD clamp circuit of FIG. 1 frequently limits where in an IC the circuit may be placed. Assume an IC with a large number of perimeter input/output (I/O) and power supply wire bond pads. In a typical arrangement, large banks of up to twenty I/O circuits (I/O pads and their associated circuitry) are placed. Power pads, which connect to on-chip power supply rails, are typically placed much less frequently, in between banks of I/O circuits. To minimize overall IC area, I/O circuits in a bank are typically abutted, resulting in little or no unused area within the I/O bank. Therefore, ESD clamp circuits typically cannot be placed within banks of I/O circuits. For this reason, the ESD clamp circuits are most typically placed in the vicinity of power pads or in the IC corner regions.
FIG. 2 illustrates a typical implementation of an active MOSFET ESD clamp circuit 19 (as described in FIG. 1) in an integrated circuit 20, to protect multiple I/O circuits 12-15. While only four I/O circuits are shown in this schematic, in a typical implementation the remote ESD clamp circuit may protect a much larger bank of I/O circuits.
The lumped ESD clamp circuit 19 in FIG. 2 is connected between a positive power supply rail (VDD) 21 and a negative power supply rail (VSS) 22. As illustrated in FIG. 1, this clamp circuit contains a trigger circuit, a buffer circuit, and a large MOSFET transistor.
I/O circuit 12 in FIG. 2 includes an I/O pad 23 coupled between the VDD rail 21 and the VSS rail 22. An NMOSFET 24 is connected between the I/O pad 23 and VSS. A PMOSFET 25 is connected between the I/O pad and VDD. NMOSFET 24 serves as the output pull-down buffer while PMOSFET 25 serves as the output pull-up buffer. The gates of NMOSFET 24 and PMOSFET 25 are each connected to output pre-driver circuitry (not shown). A diode 27 has an anode connected to VSS and a cathode connected to the I/O pad. A diode 26 has an anode connected to the I/O pad and a cathode connected to VDD. I/O circuits 13-15, each identical to I/O circuit 12, are also shown in FIG. 2.
A series of resistors R1-R3, Rn, are shown on the VDD rail between each of the I/O circuits. Each resistor represents the distributed parasitic metal resistance for that segment of the VDD rail between two adjacent I/O circuits. Similar resistors may be shown on the VSS rail, but are not included in FIG. 2 in order to clarify the schematic. Note that in a typical IC application, additional I/O circuits and additional resistors, may be placed between I/O circuits 14 and 15 in FIG. 2.
Integrated circuits are often most susceptible to damage during positive ESD events coupled onto an I/O pad referenced to grounded VSS. The primary intended ESD dissipation path for this event applied to I/O pad 23 in FIG. 2 is as follows. The I/O pad voltage rises rapidly as the positive ESD event is applied. Diode 26 forward biases, allowing the VDD power rail voltage to increase as well. The trigger circuit in lumped ESD clamp circuit 19 senses the ESD event, and, via the buffer circuit, turns on the large NMOSFET shunting device. This allows the transient ESD current to flow harmlessly between the VDD and VSS, protecting fragile elements in the I/O circuit. During this ESD event, the I/O pad 23 voltage rises to a peak level set by the sum of the voltage drops as the peak current of the applied ESD event flows through the intended dissipation path. Note that if an equivalent ESD event is applied in turn to each of the I/O pads in FIG. 2, the I/O pad most distant from the lumped ESD clamp circuit will reach the highest peak voltage. This is due to the larger number of series resistors on the VDD power supply rail between the stressed I/O pad and the lumped ESD clamp circuit.
NMOSFET buffer 24 provides an alternate dissipation path for the ESD event described above, and is often the most fragile device in the integrated circuit. During the ESD event, the NMOSFET 24 may conduct as a lateral parasitic NPN bipolar transistor, with the NMOSFET drain diffusion, source diffusion, and local P-type substrate region forming the lateral bipolar collector, emitter, and base regions, respectively. The parasitic bipolar transistor may be capable of conducting a fraction of the peak ESD current before failure. However, if the I/O pad voltage rises above a critical voltage threshold the device will suffer permanent thermal damage. While the magnitude of this critical voltage threshold varies considerably with design options and the semiconductor fabrication technology, values for this failure threshold typically range from seven to ten volts. Therefore, in order to protect I/O circuit 12 from ESD damage, ESD current must be shunted through the lumped ESD clamp circuit 19, in order to limit the voltage at I/O pad 23 below the critical failure voltage defined above.
A limitation with the remote ESD clamp circuit approach illustrated in FIG. 2 is that it becomes increasingly difficult to protect I/O circuit 12 with the lumped ESD clamp circuit 19, as the number of additional I/O circuits between them increases. This is due to the increasing series resistance (R1+R2+R3+ . . . +Rn) in the VDD power supply rail. As an example, assume an IC layout with an 80 micron bond pad pitch and a 22 micron VDD rail width. For a typical metal resistance of 0.07 ohm/square micron, the resultant resistance per pad (Rn) is about 0.25 ohm. If the VDD bus crosses ten (10) pads to reach the ESD clamp circuit, the net VDD bus resistance in the ESD current path will be 2.5 ohms. In the industry standard 200 V Machine Model ESD event, the peak current forced through the IC is approximately 3.0 A. With this peak current, the net VDD bus resistance alone creates an 7.5 volt drop in the ESD current dissipation path. This may exceed the critical voltage threshold for failure of the NMOSFET output buffer 24, even before including the additional voltage drops due to diode 26 and lumped ESD clamp circuit 19.
ESD performance may be improved by increasing the width of the VDD rail 21 to reduce the cumulative resistance, but this comes at the cost of increasing the size of the integrated circuit. Additional ESD clamp circuits may also be placed in parallel with clamp circuit 19, in between the I/O circuits. However, for the typical tightly packed banks of I/O circuits, space for these large clamp circuits is simply not available. To provide for this space between I/O circuits again requires increasing the size of the IC. Therefore, there is a need for an improved, more space efficient ESD clamp circuit scheme which is less sensitive to the effects of cumulative VDD rail resistance when protecting large banks of tightly packed I/O circuits. There is also a need for an ESD clamp circuit scheme which protects all the I/O circuits equally, without the variability seen with varying distance from the lumped ESD clamp circuit as illustrated in FIG. 2. Finally there is a need for an ESD clamp circuit scheme which is highly flexible and modular so that the same approach may be applied to multiple IC designs with only minimal concern for VDD rail resistance or the number of I/O circuits in an I/O bank.